1. Field of the Invention
The present invention relates to a method for operating a flash memory, more specifically, to a method for programming, erasing and reading a single-transistor P-channel flash memory.
2. Description of the Prior Art
For the past decade, technology and application of flash memory cells has gradually expanded with an increase of portable devices. Since portable devices usually use batteries as a power source, reduction in energy dissipation and operating the flash memory cell at optimum conditions are main areas of research in memory cell development. Generally, the flash memory cell is divided into a P-channel and an N-channel. The P-channel flash memory cell has characteristics of low power consumption, low programming voltage, and fast programming, so that the P-channel flash memory cell has been adapted to be used in a field of portable devices. Programming methods for the P-channel flash memory cell can be divided into three kinds: channel hot hole induced hot electron programming, band-to-band tunneling (BTBT), and Fowler-Nordheim (FN) tunneling.
In 1992, Hsu et al. in an article entitled xe2x80x9cA High Speed, Low Power P-Channel Flash EEPROM Using Silicon Rich Oxide as Tunneling Dielectricxe2x80x9d, International Conference on Solid State Devices and Materials (SSDM), 1992, pp.140-142, which is incorporated herein by reference, disclosed that by using silicon rich oxide (SRO) as tunneling dielectric in P-channel EEPROM cell, a high speed, low power and low voltage flash EEPROM can be accomplished. The hot electron injection in P-channel cell can be 2 orders in magnitude greater than that in N-channel cell, while the channel current during programming in P-channel cell is 2 orders in magnitude less than that in N-channel cell.
T. Ohnakado et al. in an article entitled xe2x80x9cNovel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cellxe2x80x9d, IEEE International Electron Devices Meeting Technical Digest, 1995, pp.279-282, disclosed a PMOS floating gate (FG) memory cell. A PMOS FG cell is formed in an N-well region of a P substrate. A P+ source and a P+ drain are formed in the N-well region. Dopants of the N typeare implanted into a channel region to realize an enhancement mode device. An N type polysilicon floating gate is insulated from the N-well region by a tunneling oxide layer. A control gate is insulated from the floating gate by another insulating layer. The cell is programmed by applying a high positive voltage of about 10 volts to the control gate, approximately xe2x88x926 volts to the P+ drain, floating the P+ source, and grounding the N-well region. Under these bias conditions, hot electrons induced by band-to-band tunneling (BTBT) are injected into the floating gate. The resultant accumulation of charge on the floating gate increases the threshold voltage VT of the cell to approximately xe2x88x922.5 volts. Thus, when programmed, the cell operates as an enhancement mode device.
Please refer to FIG. 1. FIG. 1 is a cross-sectional diagram of a prior art typical P-channel flash memory cell 10xe2x80x2 in a programming mode. As shown in FIG. 1, the P-channel flash memory cell 10xe2x80x2 is comprised of an N-type doped substrate 12xe2x80x2, an N-type doped control gate 14xe2x80x2, an N-type doped floating gate 16xe2x80x2, a P+ source 17xe2x80x2, a P+ drain 18xe2x80x2, a tunneling oxide layer 21xe2x80x2 located between the floating gate 16xe2x80x2 and the substrate 12xe2x80x2, and an oxide-nitride-oxide (ONO) dielectric layer 22xe2x80x2 located between the control gate 14xe2x80x2 and the floating gate 16xe2x80x2.
In a general band-to-band tunneling (BTBT) programming mode, a positive high voltage of 10 volts is provided to the control gate 14xe2x80x2, a negative voltage of xe2x88x926 volts is provided to the drain 18xe2x80x2, the substrate 12xe2x80x2 in grounded, and the source 17xe2x80x2 is in a floating state. In programming mode, electron-hole pairs are generated by band-to-band tunneling in a region where the drain 18xe2x80x2 and the floating gate 16xe2x80x2 overlap. The generated electrons are repelled into the channel region under the floating gate 16xe2x80x2. Some electrons get enough energy to overcome an energy barrier of the tunneling oxide layer 21xe2x80x2 and inject into the floating gat 16xe2x80x2. Please note that programming efficiency and tunneling probability of electrons of the BTBT mechanism are related to an energy gap in the valance band-conduction band (EV-EC) in the region where the drain 18xe2x80x2 and the floating gate 16xe2x80x2 overlap. The smaller the energy gap is, the greater the band-to-band tunneling probability of electrons will be present.
It is a primary objective of the present invention to provide a low-voltage program, read and erase method for P-channel single-transistor flash memory cell.
According to the claimed invention, a method for programming a PMOS single-transistor memory unit is disclosed. The PMOS single-transistor memory unit is comprised of a silicon dioxide-silicon nitride-silicon dioxide (ONO) dielectric stack disposed on an N-well, a P type polysilicon gate disposed on the ONO dielectric stack, a P type doped source region disposed in the N-well at one side of the P type polysilicon gate, and a P type doped drain region disposed in the N-well on the other side of the P type polysilicon gate. The method comprises: biasing said P type polysilicon gate of said PMOS single-transistor memory unit to a word line voltage VWL; biasing said P type doped source region of said PMOS single-transistor memory unit to a source line voltage VSL that is greater than the word line voltage VWL, wherein |VWLxe2x88x92VSL| is larger than threshold voltage of said PMOS single-transistor memory unit, so as to provide an adequate gate-to-source bias to turn on a P-channel 16 of said PMOS single-transistor memory unit; biasing said P type doped drain region of said PMOS single-transistor memory unit to a bit line voltage VBL, wherein said bit line voltage VBL is smaller than said source line voltage VSL, so as to provide a lateral electric field for P-channel hot holes, wherein said lateral electric field forces said P-channel hot holes passing through said P-channel in an accelerated drifting rate to said P type doped drain region, thereby inducing hot electrons near said P type doped drain region, and wherein some of induced hot electrons inject into said ONO dielectric stack; and biasing said N-well to a well voltage VNW, wherein said well voltage VNW is equal to said source line voltage VSL.
In accordance with one preferred embodiment of this invention, the word line voltage VWL is between 0xcx9c4V, the source line voltage VSL is between 3xcx9c5V, the bit line voltage VBL is 0V, and the well voltage VNW is between 3xcx9c5V. In accordance with another preferred embodiment of this invention, the word line voltage VWL is between xe2x88x921xcx9cxe2x88x925V, the source line voltage VSL is 0V, the bit line voltage VBL is between xe2x88x923xcx9cxe2x88x925V, and the well voltage VNW is between 0V.
According to one aspect of the present invention, a method for programming a PMOS single-transistor memory unit based on band-to-band tunneling mechanism is disclosed. The PMOS single-transistor memory unit is comprised of a silicon dioxide-silicon nitride-silicon dioxide (ONO) dielectric stack disposed on an N-well, a P type polysilicon gate disposed on the ONO dielectric stack, a P type doped source region disposed in the N-well at one side of the P type polysilicon gate, and a P type doped drain region disposed in the N-well on the other side of the P type polysilicon gate. The method comprises: biasing said P type polysilicon gate of said PMOS single-transistor memory unit to a word line voltage VWL greater than 0V; floating said P type doped source region of said PMOS single-transistor memory unit; and biasing said P type doped drain region of said PMOS single-transistor memory unit to a bit line voltage VBL and biasing said N-well to a well voltage VNW, wherein VNWxe2x88x92VBL bias greater than 0V. For example, the word line voltage VWL is between 2xcx9c8V, the bit line voltage VBL is xe2x88x923xcx9cxe2x88x926V, and the well voltage VNW is between 0xcx9c5V.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.